Semiconductor integrated circuit device

ABSTRACT

A semiconductor integrated circuit device of improved wireability, fewer number of wiring layers and strengthened power supply includes a plurality of power pads placed on a semiconductor chip and a plurality of signal pads placed on the semiconductor chip and configured to have a width less than that of the power pads. The signal pads and the power pads are placed in the uppermost wiring layer among a plurality of wiring layers. Signal wiring connecting I/O cells and signal pads is disposed in the uppermost wiring layer. First power wiring electrically connecting the I/O cells and first power pads is disposed in the uppermost wiring layer. Second power wiring connecting internal circuits and second power pads is disposed in the uppermost wiring layer.

FIELD OF THE INVENTION

This invention relates to a semiconductor integrated circuit device and,more particularly, to a semiconductor integrated circuit device in whicha plurality of power pads and signal pads are disposed on asemiconductor integrated circuit chip.

BACKGROUND OF THE INVENTION

A semiconductor integrated circuit device usually has plurality ofinsulating layers and a plurality of wiring layers build upalternatingly on a semiconductor integrated circuit chip. The wiringlayers are interconnected by vias, and a plurality of power pads and aplurality of signal pads are disposed on the uppermost wiring layeramong the wiring layers. The IC chip has an internal circuit or circuitsplaced in an internal area, and a plurality of I/O cells (I/O buffers)disposed peripheral to or in close proximity thereto. The internalcircuits are electrically connected to corresponding I/O cells throughwiring, and the I/O cells are electrically connected to the signal padsand power pads through wiring. The signal pads and power pads areelectrically connected to the exterior of the IC chip.

In such a semiconductor integrated circuit device disclosed heretofore,a single power pad (PVDD, PGND) and a plurality of I/O cells disposed onan IC chip are connected by respective ones of a plurality ofindependent wiring traces (H2, HD, H1) of identical thickness, theplurality of I/O cells are connected to corresponding signal pads (PSIG)by respective ones of independent wiring traces (HS), and the signalpads (PSIG) are arrayed in the area between the power pad and theplurality of I/O cells (see FIG. 6, Patent Document 1). Such anarrangement has the advantage of high packing density and enables thedegree of freedom of layout design to be raised without the formation ofthick power wiring.

[Patent Document 1] Japanese Patent Kokai Publication No.JP-P2005-93575A (FIG. 3)

SUMMARY OF THE DISCLOSURE

The above mentioned Patent Document is herein incorporated by referencethereto.

However, this conventional semiconductor integrated circuit device hascertain problems. The following analyses are given by the presentinvention.

A first problem is risk of an increase in the number of wiring layers onthe IC chip. More specifically, in the conventional semiconductorintegrated circuit device, the size of the signal pad (PSIG) is large,just as is the size of the power pad (PVDD, PGND), and hence the area inwhich it is possible to perform wiring in the uppermost wiring layer isdiminished (i.e., wiring sources are diminished). Consequently, there isthe danger that the wiring layers will increase by two for thesignal-pad wiring (HS) and power-pad wiring (H2, HD, H1).

A second problem is risk of a decline in wireability (freedom ofwiring). More specifically, in the conventional semiconductor integratedcircuit device, the power pad (PVDD, PGND) is disposed remote from theI/O cells. Therefore, in order to lower the resistance (strengthen) thewiring (H2, HD, H1) for the power pad, there is an increase in thenumber of wiring traces. This has the risk of diminishing wireability.

A third problem is risk of a decline in degree of freedom regardingplacement of macros such as internal circuits in the area underlying thesignal pads. More specifically, in the conventional semiconductorintegrated circuit device, the power wiring (HD) electrically connectingthe I/O cells and power pad (PVDD, PGND) is disposed below the signalpads (PSIG). Consequently, it may be difficult to dispose a macro, whichuses an (n−1)th wiring layer, below the signal pad (PSIG) in theuppermost wiring layer (nth wiring layer).

A fourth problem is risk of an increase in the voltage drop of the powersource of the internal circuits. More specifically, in the conventionalsemiconductor integrated circuit device, the power wiring (HD)connecting the I/O cells and the power pad is disposed directly belowthe signal pads (PSIG). Consequently, power wiring density for supplyingthe internal circuits declines and resistance increases.

Accordingly, it is an object of the present invention to enable animprovement in wireability in a semiconductor integrated circuit device,a reduction in number of wiring layers and strengthening of the powersupply.

According to a first aspect of the present invention, there is provideda semiconductor integrated circuit device comprising a plurality ofpower pads laid out on a semiconductor chip; and a plurality of signalpads laid out on the semiconductor chip and configured to have a widthless than that of the power pads.

The following modes may be implemented according to the presentinvention.

The power pads may be square pads and the signal pads are rectangularpads.

The semiconductor chip may have I/O cells and internal circuits; thepower pads include first power pads for the I/O cells and second powerpads for the internal circuits; the first power pads are placed on or inthe vicinity of the I/O cells; and the second power pads are placed onthe internal circuits.

The internal circuits may be placed at the center of the semiconductorchip, and the I/O cells are placed in the vicinity of an outer edge ofthe semiconductor chip.

The signal pads and the power pads may be placed in an uppermost wiringlayer among a plurality of wiring layers.

At least one portion of signal wiring electrically connecting the I/Ocells and the signal pads may be placed in the uppermost wiring layer.

At least one portion of first power wiring electrically connecting theI/O cells and the first power pads may be placed in the uppermost wiringlayer.

At least one portion of second power wiring electrically connecting theinternal circuits and the second power pads may be placed in theuppermost wiring layer.

The signal pads may be placed in order starting from the vicinity of theouter edge of the semiconductor chip while the first power pads areavoided.

The device may further comprise a plurality of bumps disposed onrespective ones of the power pads and the signal pads; wherein the bumpsare approximately the same in size.

The portion of the first power wiring placed in the uppermost wiringlayer may be routed along the outer edge of the semiconductor chip; andat least some of the signal pads are pads that are placed on the I/Ocells and that have a width of diminished size in a direction at rightangles to the outer edge of the semiconductor chip.

At least a portion of the second power wiring placed in the uppermostwiring layer may be routed in a direction at right angles to the outeredge of the semiconductor chip; and at least some of the signal pads arepads that are placed between wiring traces of the second power wiring onthe internal circuits and that have a width of diminished size in adirection parallel to the outer edge of the semiconductor chip.

The device may further comprise a pair of power wiring traces routed inparallel in the same direction from both ends of two opposing sides ofone power pad from among the plurality of power pads; wherein theplurality of signal pads include a first signal pad interposed betweenthe pair of power wiring traces; and the first signal pad has a widththat is smaller than spacing between the first pair of power wiringtraces.

The plurality of signal pads may include a second signal pad interposedbetween one wiring trace among the pair of power wiring traces andplaced in an area that does not interfere with the first signal pad; thesecond signal pad is connected to second signal wiring; the plurality ofpower pads, the first and second signal pads, the pair of power wiringtraces and the second signal wiring are arranged using the same wiringlayer; and the second signal wiring is a wiring that passes between thefirst signal pad and the pair of power wiring traces.

The spacing between the pair of power wiring traces may be less than aspacing between the two opposing sides of the power pad

The meritorious effects of the present invention are summarized asfollows.

In accordance with the present invention (claims 1 to 15), pads ofoptimum sizes are employed in accordance with amount of current passed.Therefore, by optimizing layout of pads of different sizes, it ispossible to improve wireability of the uppermost wiring layer, reducethe number of wiring layers and strengthen the power supply.

Other features and advantages of the present invention will be apparentfrom the following description taken in conjunction with theaccompanying drawings, in which like reference characters designate thesame or similar parts throughout the figures thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view schematically illustrating a bump layout surfaceof a semiconductor integrated circuit device according to a firstexample of the present invention;

FIG. 2 is a partially enlarged plan view schematically illustrating padsand wiring patterns in a region enclosed by a phantom line in thesemiconductor integrated circuit device according to the first example;

FIG. 3 is a partial plan view schematically illustrating only patternsof an uppermost wiring layer of the semiconductor integrated circuitdevice according to the first example;

FIG. 4 is a partial sectional view taken along line X-X′ of FIG. 2schematically illustrating the semiconductor integrated circuit deviceaccording to the first example;

FIG. 5 is a partial sectional view taken along line Y-Y′ of FIG. 2schematically illustrating the semiconductor integrated circuit deviceaccording to the first example; and

FIG. 6 is a wiring layout view illustrating the connections between I/Ocells and pads in a semiconductor integrated circuit device according toan example of the related art.

PREFERRED MODES OF THE INVENTION First Example

A semiconductor integrated circuit device according to a first exampleof the present invention will now be described.

FIG. 1 is a plan view schematically illustrating a bump layout surfaceof a semiconductor integrated circuit device according to a firstexample of the present invention, FIG. 2 is a partially enlarged planview schematically illustrating pads and wiring patterns in a regionenclosed by a phantom line in the semiconductor integrated circuitdevice according to the first example, FIG. 3 is a partial plan viewschematically illustrating only patterns of an uppermost wiring layer ofthe semiconductor integrated circuit device according to the firstexample, FIG. 4 is a partial sectional view taken along line X-X′ ofFIG. 2 schematically illustrating the semiconductor integrated circuitdevice according to the first example, and FIG. 5 is a partial sectionalview taken along line Y-Y′ of FIG. 2 schematically illustrating thesemiconductor integrated circuit device according to the first example.

A semiconductor integrated circuit device 1 is a semiconductor chiphaving internal circuits and I/O cells. As illustrated in FIG. 1, bumps(soldering holes) 2 are disposed on a bump layout surface of thesemiconductor integrated circuit device 1 at locations indicated by thecircle marks on the grid. Pads (not shown) are placed below the bumps 2.The bump layout surface has an internal circuit area 1 a disposed at thecenter of the surface and an I/O cell area 1 b in the proximity of (orsurrounding) the internal circuit area 1 a. The internal circuit area 1a is an area in which a plurality of internal circuits (not shown) areplaced within the semiconductor integrated circuit device 1. The I/Ocell area 1 b is an area in which a plurality of I/O cells (not shown)are placed within the semiconductor integrated circuit device 1. Thesemiconductor integrated circuit device 1 has a multi-layered wiringarrangement in which a plurality of insulating layers 3, 5 and 8 (FIGS.4 and 5) and a plurality of wiring layers 4 and 7 (FIGS. 4 and 5) arebuilt up alternatingly on a semiconductor substrate 10 (FIGS. 4 and 5),with the wiring layers (not shown) being connected by vias. It should benoted that the pattern of the internal circuit area 1 a and I/O cellarea 1 b illustrated in FIG. 1 is one example, and a plurality of setsof internal circuit areas and I/O cell areas may be laid out. Pads andwiring patterns in a region enclosed by a phantom line in FIG. 1 areillustrated in FIG. 2.

The multi-layered wiring arrangement of the semiconductor integratedcircuit device 1 has an uppermost wiring layer 4 and a wiring layer 7,as illustrated in FIG. 2.

The uppermost wiring layer 4 is the uppermost layer (toward the side ofthe bumps) among the multiple wiring layers and is disposed between theinsulating layers 3 and 5, as illustrated in FIGS. 4 and 5. Theuppermost wiring layer 4 has signal pads 4 a, a first VDD pad 4 b, afirst GND pad 4 c, signal wiring 4 d, first VDD wiring 4 e, first GNDwiring 4 f, second VDD pads 4 g, second GND pads 4 h, second VDD wiring4 i and second GND wiring 4 j.

The signal pads 4 a are signal pads for I/O cells 1 c. The signal pads 4a are disposed below bumps 2 (FIG. 1) at prescribed locations amonglocations marked by the circles on the grid in FIG. 1 in the internalcircuit area 1 a and I/O cell area 1 b. The signal pads 4 a are arrangedin order from the outer edge of the semiconductor integrated circuitdevice 1 while the first VDD pad 4 b and first GND pad 4 c are avoided.The signal pads 4 a are constructed as an integral part of thecorresponding signal wiring 4 d in the same layer, as illustrated inFIG. 3. The signal pad 4 a is electrically connected to a diffusionlayer 10 a, which serves as the signal terminal of the corresponding I/Ocell 1 c, through the signal wiring 4 d, a via 6 a, signal wiring 7 aand a via 9 a, as illustrated in FIG. 4. The signal pad 4 a isconfigured to have a width (along the transverse direction of the pad)smaller than that of the power pads (first VDD pad 4 b, first GND pad 4c, second VDD pad 4 g, second GND pad 4 h). For example, the signal pads4 a can be made polygonal in shape, such as rectangular or octagonal.The reason for this is that only a current smaller than that of thepower pads flows through the signal pad 4 a. By way of example, thelongitudinal direction of the signal pads 4 a can be oriented inparallel with the outer edge of the semiconductor integrated circuitdevice 1 with regard to the signal pad 4 a of I/O cell area 1 b, whileit can be oriented perpendicular to the outer edge of the semiconductorintegrated circuit device 1 with regard to the signal pad 4 a ofinternal circuit area 1 a, in accordance with the power pads (first VDDpad 4 b, first GND pad 4 c, second VDD pad 4 g, second GND pad 4 h) andpatterns of the wiring thereof (first VDD wiring 4 e, first GND wiring 4f, second VDD wiring 4 i and second GND pad 4 h). Power wiring (firstVDD wiring 4 e, first GND wiring 4 f, second VDD wiring 4 i and secondGND wiring 4 j) is not disposed directly below the signal pads 4 a.

Although the signal pads 4 a are small in width, no problems arisebecause the size thereof is sufficient for the allowable current of theI/O cells. Further, the bumps 2 disposed on the signal pads 4 a are ofapproximately the same size as the bumps 2 disposed on the power pads(first VDD pad 4 b, first GND pad 4 c, second VDD pad 4 g, second GNDpad 4 h). Further, by using pads having an area of larger width thanthat of the signal pads 4 a as the power pads through which a largecurrent flows, the area of contact with the bumps can be enlarged andhence there is no increase in connection resistance.

The first VDD pad 4 b is a VDD-side power pad for the I/O cells 1 c. Thefirst VDD pad 4 b is disposed below bumps 2 (FIG. 1) at prescribedlocations among locations marked by the circles on the grid in FIG. 1 inthe internal circuit area 1 a. It should be noted that the first VDD pad4 b preferably is disposed at a location in the vicinity of the I/O cellarea 1 b or inside the I/O cell area 1 b. The first VDD pad 4 b isconstructed as an integral part of the first VDD wiring 4 e (VDD bus) inthe same layer. The first VDD pad 4 b is electrically connected to afirst VDD terminal 10 b of each I/O cell through the first VDD wiring 4e, a via (not shown; an area that will not interfere with the via 6 a inthe same layer), VDD wiring (not shown; an area that will not interferewith signal wiring 7 a in the same layer) and a via (not shown; an areathat will not interfere with the via 9 a in the same layer). Inconsideration of the fact that a large current will flow through it, thefirst VDD pad 4 b is configured to have a width larger than that of thesignal pads 4 a. For example, the first VDD pad 4 b can be madepolygonal in shape, such as square or octagonal.

The first GND pad 4 c is a GND-side power pad for the I/O cells 1 c. Thefirst GND pad 4 c is disposed below the bump 2 (FIG. 1) at prescribedlocations among locations marked by the circles on the grid in FIG. 1 inthe I/O cell area 1 b. It should be noted that the first GND pad 4 cpreferably is disposed at a location in the vicinity of the outer edgeof the semiconductor integrated circuit device 1. The first GND pad 4 cis constructed as an integral part of the first GND wiring 4 f (GND bus)in the same layer. The first GND pad 4 c is electrically connected to adiffusion layer 10 c, which serves as a first GND terminal of each I/Ocell, through the first GND wiring 4 f, a via 6 b, first GND wiring 7 band a via 9 b, as illustrated in FIG. 5. In consideration of the factthat a large current will flow through it, the first GND pad 4 c isconfigured to have a width larger than that of the signal pads 4 a. Forexample, the first GND pad 4 c can be made polygonal in shape, such assquare or octagonal.

The signal wiring 4 d is constructed as an integral part of thecorresponding signal pad 4 a in the same layer and is mainly disposed inthe internal circuit area 1 a. The first VDD wiring 4 e (VDD bus) isconstructed as an integral part of the first VDD pad 4 b in the samelayer and is mainly disposed in the I/O cell area 1 b. The first GNDwiring 4 f (GND bus) is constructed as an integral part of the first GNDpad 4 c in the same layer and is mainly disposed in the I/O cell area 1b. The wiring traces of the signal wiring 4 d, first VDD wiring 4 e andfirst GND wiring 4 f preferably are disposed in the uppermost layer tothe greatest extent possible while interference with power pads (firstVDD pad 4 b, first GND pad 4 c, second VDD pad 4 g, second GND pad 4 h)is avoided. The signal wirings 4 d preferably are laid out by automaticrouting. Further, although the wiring traces of the first VDD wiring 4 eand first GND wirings 4 f are laid out as special-purpose patterns, theymay be laid out by automatic wiring if possible.

The second VDD pads 4 g are VDD-side power pads for the internalcircuits. The second VDD pad 4 g is disposed below the bump 2 (FIG. 1)at prescribed locations among locations marked by the circles on thegrid in FIG. 1 in the internal circuit area 1 a. The second VDD pad 4 gis constructed as an integral part of the second VDD wiring 4 i (VDDbus) in the same layer. The second VDD pad 4 g is electrically connectedto a second VDD terminal 10 d of the internal circuit through the secondVDD wiring 4 i, a via (not shown; an area that will not interfere withthe via 6 b in the same layer), VDD wiring (not shown; an area that willnot interfere with the GND wiring 7 b in the same layer) and a via (notshown; an area that will not interfere with the via 9 b in the samelayer). It should be noted that the second VDD terminal 10 d is disposeddirectly below or peripheral to the second VDD wiring 4 i. Inconsideration of the fact that a large current will flow through it, thesecond VDD pad 4 g is configured to have a width larger than that of thesignal pads 4 a. For example, the first VDD pad 4 b can be madepolygonal in shape, such as square or octagonal.

The second GND pad 4 h is a GND-side power pad for the internal circuit.The second GND pad 4 h is disposed below the bump 2 (FIG. 1) atprescribed locations among locations marked by the circles on the gridin FIG. 1 in the I/O cell area 1 b. The second GND pad 4 h isconstructed as an integral part of the second GND wiring 4 j (GND bus)in the same layer. The second GND pad 4 h is electrically connected to asecond GND terminal 10 e through the second GND wiring 4 j, a via (notshown; an area that will not interfere with the via 6 b in the samelayer), GND wiring (not shown; an area that will not interfere with theGND wiring 7 b in the same layer) and a via (not shown; an area thatwill not interfere with the via 9 b in the same layer). It should benoted that the second GND terminal 10 e is disposed directly below orperipheral to the second GND wiring 4 j. In consideration of the factthat a large current will flow through it, the second GND pad 4 h isconfigured to have a width larger than that of the signal pads 4 a. Forexample, the first VDD pad 4 b can be made polygonal in shape, such assquare or octagonal.

The second VDD wiring 4 i (VDD bus) is configured as an integral part ofthe second VDD pad 4 g in the same layer and is disposed in the internalcircuit area 1 a. The second GND wiring 4 j (GND bus) is configured asan integral part of the second GND pad 4 h in the same layer and isdisposed in the internal circuit area 1 a. The wiring traces of thesecond VDD wiring 4 i and second GND wiring 4 j are extended from thepads to the vicinity of the I/O cell area 1 b using the uppermost wiringlayer 4 in order to reinforce the power supply.

The wiring layer 7 is placed one level below the uppermost wiring layer4 among the multiple wiring layers and is disposed between theinsulating layers 5 and 8, as illustrated in FIGS. 4 and 5. The wiringlayer 7 has the first signal wiring 7 a, first VDD wiring (not shown),the GND wiring 7 b, second VDD wiring (not shown) and second GND wiring(not shown). Each of the wiring traces is for electrically connectingthe corresponding wiring of the uppermost wiring layer 4 and terminal.

In the first example illustrated in FIGS. 2 and 3, the power wiringemploys the wiring having a width larger than that of the signal wiring.At the time of filing of Patent Document 1, the mixing of wiring traceshaving different width dimensions resulted in a complicated design flow,and this was an obstacle particularly in terms of advancing automaticdesign. However, the present inventors have found that if use is made ofautomatic layout in a case where wiring traces of large and small widthsare mixed, as disclosed in the specification of Japanese Patent KokaiPublication No. JP-P2004-350946A (the entire disclosure thereof beingincorporated herein by reference thereto), it is possible to implementautomatic design using wiring thicker than that of the signal wiring forthe power wiring. In particular, reducing the width of the signal pads 4a laid out in the internal circuit area 1 a, as illustrated in FIGS. 2and 3, makes it possible to enlarge the wiring width of the power wiring4 i, 4 j for the internal circuits without enlarging the layout area,and a fluctuation in potential in the internal circuits can be reduced.

Further, owing to use of a signal pad of small width also for the signalpad 4 a disposed in the I/O cell area 1 b, a fluctuation in potential inthe I/O cells and internal circuits can be reduced by strengthening thepower wiring 4 e, 4 f for the I/O cells, the signal wiring 4 d betweenthe I/O cells and pads, the power wiring 4 i for the internal circuitsand the signal wiring (not shown) for the internal circuits. Anadditional effect is that the reliability of EM, etc., is enhanced bystrengthening the power wiring.

Further, since the wiring traces of the power wiring 4 i, 4 j are laidout at right angles to the outer edge of the semiconductor chip in theinternal circuit area 1 a, the signal pads 4 a disposed in the internalcircuit area 1 a are arranged in such an orientation that the widththereof in the direction parallel to the outer edge of the semiconductorchip is reduced so as to facilitate the routing of the power wiring 4 i,4 j. In the I/O cell area 1 b, on the other hand, the power wiring 4 e,4 f is routed along the outer edge of the semiconductor chip.Accordingly, the signal pad 4 a disposed in the I/O cell area 1 b isarranged in such an orientation that the width thereof at right anglesto the outer edge of the semiconductor chip is reduced so as not toobstruct the routing of the power wiring 4 e, 4 f.

Further, in FIGS. 4 and 5, the wiring layer underlying the uppermostwiring layer 4 in the multi-layer wiring arrangement is solely thewiring layer 7. However, multiple wiring layers may be disposed belowthe uppermost wiring layer 4. Furthermore, in FIGS. 2 and 3, it is alsopossible to use the vacant area in the uppermost layer to strengthen thepower wiring. Further, although the bumps are illustrated as beingformed by solder holes in the first example, it goes without saying thata suitable material can be selected as the material constituting thebumps.

Further, in FIGS. 2 and 3, pad sizes of two types are employed inaccordance with the allowable amount of current. However, pads of alarger number of sizes may be used.

The first example affords a number of meritorious effects, which willnow be described.

First, wireability (wiring ability) is improved. In other words, byusing pads having a width less than that of the power pads (the firstVDD pad 4 b, first GND pad 4 c, second VDD pad 4 g, second GND pad 4 h)for the signal pads 4 a, the wireable area between the signal pads 4 ain the uppermost wiring layer 4 is enlarged and wireability enhanced.Further, by placing the power pads (first VDD pad 4 b and first GND pad4 c) for the I/O cells 1 c in the vicinity of the I/O cell area 1 b orin a region within the I/O cell area 1 b, pressure upon the wireablearea between signal pads 4 a is relieved and wireability improved.

Second, the number of wiring layers can be reduced. In other words, byusing pads having a width less than that of the power pads (the firstVDD pad 4 b, first GND pad 4 c, second VDD pad 4 g, second GND pad 4 h)for the signal pads 4 a, it becomes possible to lay out the signalwiring 4 d using mainly the uppermost wiring layer 4 in the internalcircuit area 1 a. The frequency of use of the signal wiring 7 a in thewiring layer 7 one level below the uppermost wiring layer 4 is reducedin the internal circuit area 1 a (even if used it is only in the I/Ocell area 1 b and vicinity thereof), and a reduction in the height ofthe layers can be achieved. Further, since the wiring layer one levelbelow the uppermost wiring layer is a strong wiring layer whose role isto strengthen the power supply, the wiring layer one level below theuppermost wiring layer can also be eliminated if power can be suppliedby another wiring layer.

Third, strengthening of the power supply of the I/O cells 1 c and areduction in power supply noise can be achieved. The reason for this isthat by placing the power pads (first VDD pad 4 b and first GND pad 4 c)on or in the vicinity of the I/O cells 1 c, wiring resistance betweenthe power pads can be minimized.

Fourth, strengthening of the power supply of the internal circuits and areduction in power supply noise can be achieved. The reason for this isthat by using pads having a width less than that of the power pads (thefirst VDD pad 4 b, first GND pad 4 c, second VDD pad 4 g, second GND pad4 h) for the signal pads 4 a, a wiring area for supplying the power ofthe internal circuits can be acquired.

Degree of freedom of macro placement below the signal pads 4 a in theinternal circuit area 1 a is enhanced. The reason for this is that sincethe signal wiring 4 d is formed using mainly the uppermost wiring layer4 in the internal circuit area 1 a and the frequency of use of thesignal wiring 7 a in the wiring layer 7 is reduced, the area in whichplacement of a macro below the signal pads 4 a in the internal circuitarea 1 a is enlarged.

As many apparently widely different examples of the present inventioncan be made without departing from the spirit and scope thereof, it isto be understood that the invention is not limited to the specificexamples thereof except as defined in the appended claims.

It should be noted that other objects, features and aspects of thepresent invention will become apparent in the entire disclosure and thatmodifications may be done without departing the gist and scope of thepresent invention as disclosed herein and claimed as appended herewith.

Also it should be noted that any combination of the disclosed and/orclaimed elements, matters and/or items may fall under the modificationsaforementioned.

1. A semiconductor integrated circuit device comprising: a plurality ofpower pads placed on a semiconductor chip; and a plurality of signalpads placed on the semiconductor chip and configured to have a widthless than that of said power pads, wherein the plurality of signal padsinclude a first signal pad positioned in a first direction and a secondsignal pad positioned in a second direction different from the firstdirection.
 2. The device according to claim 1, wherein said power padsare square pads and said signal pads are rectangular pads.
 3. The deviceaccording to claim 1, wherein the semiconductor chip has I/O cells andinternal circuits; said power pads include first power pads for said I/Ocells and second power pads for said internal circuits; said first powerpads are placed on or in the vicinity of said I/O cells; and said secondpower pads are placed on said internal circuits.
 4. The device accordingto claim 3, wherein said internal circuits are placed at the center ofthe semiconductor chip, and said I/O cells are placed in the vicinity ofan outer edge of the semiconductor chip.
 5. The device according toclaim 1, wherein said signal pads and said power pads are placed in anuppermost wiring layer among a plurality of wiring layers.
 6. The deviceaccording to claim 3, wherein at least one portion of signal wiringelectrically connecting said I/O cells and said signal pads is placed inthe uppermost wiring layer.
 7. The device according to claim 3, whereinat least one portion of first power wiring electrically connecting saidI/O cells and said first power pads is placed in the uppermost wiringlayer.
 8. The device according to claim 3, wherein at least one portionof second power wiring electrically connecting said internal circuitsand said second power pads is placed in the uppermost wiring layer. 9.The device according to claim 4, wherein said signal pads are placed inorder starting from the vicinity of the outer edge of the semiconductorchip while said first power pads are avoided.
 10. The device accordingto claim 1, further comprising a plurality of bumps disposed onrespective ones of said power pads and said signal pads; wherein saidbumps are approximately the same in size.
 11. The device according toclaim 7, wherein the portion of the first power wiring placed in theuppermost wiring layer is routed along the outer edge of thesemiconductor chip; and at least some of said signal pads are pads thatare placed on said I/O cells and that have a width of diminished size ina direction at right angles to the outer edge of the semiconductor chip.12. The device according to claim 8, wherein at least a portion of thesecond power wiring placed in the uppermost wiring layer is routed in adirection at right angles to the outer edge of the semiconductor chip;and at least some of the signal pads are pads that are placed betweenwiring traces of the second power wiring on the internal circuits andthat have a width of diminished size in a direction parallel to theouter edge of the semiconductor chip.
 13. The device according to claim1, further comprising a pair of power wiring traces routed in parallelin the same direction from both ends of two opposing sides of one powerpad from among the plurality of power pads; wherein said first signalpad is interposed between said pair of power wiring traces; and saidfirst signal pad has a width that is smaller than spacing between saidfirst pair of power wiring traces.
 14. The device according to claim 13,wherein said second signal pad is interposed between one wiring traceamong said pair of power wiring traces and placed in an area that doesnot interfere with said first signal pad; said second signal pad isconnected to second signal wiring; said plurality of power pads, saidfirst and second signal pads, said pair of power wiring traces and saidsecond signal wiring are arranged using the same wiring layer; and saidsecond signal wiring is a wiring that passes between said first signalpad and said pair of power wiring traces.
 15. The device according toclaim 13, wherein the spacing between said pair of power wiring tracesis less than a spacing between the two opposing sides of said power pad.16. The device according to claim 1, wherein the first signal pad ispositioned perpendicular to the second signal pad.
 17. The deviceaccording to claim 1, wherein the semiconductor chip includes I/O cellsand internal circuits; said first signal pad corresponding to the I/Ocells; and said second signal pad corresponding to the internalcircuits.
 18. The device according to claim 17, wherein the first signalpad is positioned perpendicular to the second signal pad.